SH7751 Datasheet, PDF (37/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
19.4.1 Interrupt
Operation Sequence
Figure 19.3 Interrupt
Operation Flowchart
Page
788
Revision (See Manual for Details)
Figure amended
Yes
Level 14
No
Yes
IMASK* =
level 14 or
lower?
interrupt?
Yes
Level 1
No
Set interrupt source
in INTEVT
No _Yes
IMASK =
level 13 or
lower?
interrupt?
Yes
Save SR to SSR;
save PC to SPC
No _Yes
IMASK =
level 0?
No
Set BL, MD, RB bits
in SR to 1
Branch to exception
handler
19.6 Usage Notes
791 to
793
20.2.1 Access to UBC 798
Registers
20.3.1 Explanation of 808
Terms Relating to
Accesses
21.1.1 Features
823
Note: * IMASK: Interrupt mask bits in status register (SR)
Newly added
Description amended
2. Execute instructions requiring 5 states for execution after
the memory store instruction that updated the register. As
the CPU executes two instructions in parallel and a
minimum of 0.5 state is required for execution of one
instruction, 11 instructions must be inserted. The updated
value will be valid from the 6th state onward.
Description amended
In this LSI, all operand accesses are treated as either read
accesses or write accesses. The following instructions require
special attention:
…
This LSI handles all operand accesses as having a data size.
The data size can be byte, word, longword, or quadword. The
operand data size for the PREF, OCBP, OCBWB, MOVCA.L,
and OCBI instructions is treated as longword.
Description amended
The high-performance user debug interface (H-UDI) is a serial
input/output interface supporting a subset of the JTAG, IEEE
1149.1, IEEE Standard Test Access Port and Boundary-Scan
Architecture. …
Rev.4.00 Oct. 10, 2008 Page xxxvii of xcviii
REJ09B0370-0400