SH7751 Datasheet, PDF (598/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
14.1.2 Block Diagram (SH7751)
Figure 14.1 shows a block diagram of the DMAC.
On-chip
peripheral
module
TMU
SCI, SCIF
DACK0, DACK1
DRAK0, DRAK1
DMAC module
Count
control
SARn
Register
control
DARn
Activation
control
DMATCRn
CHCRn
Request
priority
control
DMAOR
Bus
interface
4
dreq0-3
SAR0, DAR0, DMATCR0,
CHCR0 only
DREQ0, DREQ1
DDT module
DTR command buffer
BAVL
D[31:0]
ID[1:0]
TDACK
External bus
32B data
buffer
Bus state
controller
Legend:
DMAOR: DMAC operation register
SARn:
DMAC source address
register
DARn:
DMAC destination address register
DMATCRn: DMAC transfer count register
CHCRn: DMAC channel control register
Note: n = 0 to 3
DBREQ
DDTMODE
BAVL
DDTD
id[1:0]
48 bits
tdack
CH0 CH1 CH2 CH3
Request controller
TR
DBREQ
Figure 14.1 Block Diagram of DMAC
Rev.4.00 Oct. 10, 2008 Page 500 of 1122
REJ09B0370-0400