SH7751 Datasheet, PDF (588/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
CKIO
T1
T2
Twait
T1
T2
Twait
T1
T2
A25–A0
CSm
CSn
BS
RD/WR
RD
D31–D0
Area m space read
Area n space read
Area n space write
Area m inter-access wait specification Area n inter-access wait specification
Figure 13.68 Waits between Access Cycles
13.3.11 Bus Arbitration
This LSI is provided with a bus arbitration function that grants the bus to an external device when
it makes a bus request.
There are two bus arbitration modes: master mode, and slave mode. In master mode the bus is held
on a constant basis, and is released to another device in response to a bus request. In slave mode
the bus is not held on a constant basis; a bus request is issued each time an external bus cycle
occurs, and the bus is released again at the end of the access.
Master mode and slave mode can be specified by the external mode pins. See appendix C, Mode
Pin Settings, for the external mode pin settings. In master mode and slave mode, the bus goes to
the high-impedance state when not being held. Instead of a slave mode chip. In the following
description, an external device that issues bus requests is also referred to as a slave.
This LSI has three internal bus masters: the CPU, DMAC, and PCIC. When synchronous DRAM
or DRAM is connected and refresh control is performed, refresh requests constitute a fourth bus
master. In addition to these are bus requests from external devices in master mode. If requests
Rev.4.00 Oct. 10, 2008 Page 490 of 1122
REJ09B0370-0400