SH7751 Datasheet, PDF (776/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Serial Communication Interface with FIFO (SCIF)
Bit 4—Parity Mode (O/E): Selects either even or odd parity for use in parity addition and
checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition
and checking. The O/E bit setting is invalid when parity addition and checking is disabled.
Bit 4: O/E
Description
0
Even parity*¹
(Initial value)
1
Odd parity*²
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is even. In reception, a
check is performed to see if the total number of 1-bits in the receive character plus the
parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check
is performed to see if the total number of 1-bits in the receive character plus the parity
bit is odd.
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length.
Bit 3: STOP
Description
0
1 stop bit*¹
(Initial value)
1
2 stop bits*²
Notes: 1. In transmission, a single 1-bit (stop bit) is added to the end of a transmit character
before it is sent.
2. In transmission, two 1-bits (stop bits) are added to the end of a transmit character
before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2—Reserved: This bit is always read as 0, and should only be written with 0.
Rev.4.00 Oct. 10, 2008 Page 678 of 1122
REJ09B0370-0400