SH7751 Datasheet, PDF (202/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
four instructions after the CCR update instruction. Also, a branch instruction to the P0, P1, P3, or
U0 area should be located at least eight instructions after the CCR update instruction.
• EMODE: Cache-double-mode bit
Indicates whether or not cache-double-mode is used in the SH7751R. This bit is reserved in the
SH7751. The EMODE bit cannot be modified while the cache is in use.
0: SH7751-compatible-mode*¹ (Initial value)
1: Cache-double-mode
Note: 1. Address allocation in OC index mode and RAM mode is not compatible with that in
RAM mode.
• IIX: IC index enable bit
0: Effective address bits [12:5] used for IC entry selection
1: Effective address bits [25] and [11:5] used for IC entry selection
• ICI: IC invalidation bit
When 1 is written to this bit, the V bits of all IC entries are cleared to 0. This bit always returns
0 when read.
• ICE: IC enable bit
Indicates whether or not the IC is to be used. When address translation is performed, the IC
cannot be used unless the C bit in the page management information is also 1.
0: IC not used
1: IC used
• OIX: OC index enable bit*²
0: Effective address bits [13:5] used for OC entry selection
1: Effective address bits [25] and [12:5] used for OC entry selection
Note: 2. In the SH7751R, clear the OIX bit to 0 when the ORA bit is 1.
• ORA: OC RAM enable bit*³
When the OC is enabled (OCE = 1), the ORA bit specifies whether the half of the OC are to be
used as RAM. When the OC is not enabled (OCE = 0), the ORA bit should be cleared to 0.
0: Normal mode (the entire OC is used as a cache)
1: RAM mode (half of the OC is used as a cache and the other half is used as RAM)
Note: 3. In the SH7751R, clear the ORA bit to 0 when the OIX bit is 1.
Rev.4.00 Oct. 10, 2008 Page 104 of 1122
REJ09B0370-0400