SH7751 Datasheet, PDF (15/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
5.6.1 Resets
(3) H-UDI Reset
Page
149
(4) Instruction TLB
150
Multiple-Hit Exception
(5) Data TLB Multiple- 151
Hit Exception
5.6.2 General
162
Exceptions
(11) General FPU
Disable Exception
Revision (See Manual for Details)
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
…
SR.IMASK = B'1111;
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
…
SR.IMASK = B'1111;
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
…
SR.IMASK = B'1111;
Note amended
Note: * FPU instructions are instructions in which the first 4
bits of the instruction code are H'F (but excluding
undefined instruction H'FFFD), and the LDS, STS,
LDS.L, and STS.L instructions corresponding to
FPUL and FPSCR.
Rev.4.00 Oct. 10, 2008 Page xv of xcviii
REJ09B0370-0400