SH7751 Datasheet, PDF (1015/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
22.2.34 I/O Space Base Register (PCIIOBR)
Bit:
Initial value:
PCI-R/W:
PP Bus-R/W:
31
IOBR31
0
—
R/W
30
IOBR30
0
—
R/W
29
IOBR29
0
—
R/W
28
IOBR28
0
—
R/W
27
IOBR27
0
—
R/W
26
IOBR26
0
—
R/W
25
IOBR25
0
—
R/W
24
IOBR24
0
—
R/W
Bit: 23
22
21
20
19
18
17
16
IOBR23 IOBR22 IOBR21 IOBR20 IOBR19 IOBR18 —
—
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
LOCK
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R
R
R
R
R
R
R
R/W
The I/O space base register (PCIIOBR) species the most significant 14 bits of the address of the
PCI I/O space when performing I/O read and I/O write operations by PIO transfer. It also specifies
locked transfers. This 32-bit read/write register can be accessed from the PP bus.
All bits of the PCII0BR register are initialized to 0 at a power-on reset. They are not initialized at a
software reset.
Setting bit 0 (LOCK) to 1 locks the I/O space for PIO transfers while the bit remains set. A locked
transfer consists of the combined read and write operations. Do not attempt to perform other PIO
transfers during the locked combination of read and write operations.
Rev.4.00 Oct. 10, 2008 Page 917 of 1122
REJ09B0370-0400