SH7751 Datasheet, PDF (883/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Interrupt Controller (INTC)
To clear each interrupt mask, write 1 to the corresponding bit of the INTMSKCLR00 register. The
values in INTMSK00 do not change if you write 0 to it.
Bit: 31
30
29
...
11
10
9
8
...
Initial value:
0
0
0
...
0
0
1
1
R/W: R
R
R
...
R
R
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 31 to 0—Interrupt Masks: These bits indicate the existence of an interrupt request
corresponding to each bit. For the correspondence between bits and interrupt sources, see section
19.3.7, INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation.
Bits 31 to 0
0
1
Description
Accept corresponding interrupt request
Mask corresponding interrupt request
19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00)
The interrupt mask clear register 00 (INTMSKCLR00) clears the masks for each request of the
corresponding interrupt. INTMSKCLR00 is a 32-bit write-only register.
Bit: 31
30
29
...
11
10
9
8
...
Initial value: —
—
—
...
—
—
—
—
R/W: W
W
W
...
W
W
W
W
Bit:
7
6
5
4
3
2
1
0
Initial value: —
—
—
—
—
—
—
—
R/W: W
W
W
W
W
W
W
W
Rev.4.00 Oct. 10, 2008 Page 785 of 1122
REJ09B0370-0400