SH7751 Datasheet, PDF (483/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Bits 8 to 6—Address-OE/WE Assertion Delay (A6TED2–A6TED0): These bits set the delay
time from address output to OE/WE assertion on the connected PCMCIA interface. The setting of
these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 8: A6TED2
0
1
Bit 7: A6TED1
0
1
0
1
Bit 6: A6TED0
0
1
0
1
0
1
0
1
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
Bits 5 to 3—OE/WE Negation-Address Delay (A5TEH2–A5TEH0): These bits set the address
hold delay time from OE/WE negation in a write on the connected PCMCIA interface or in an I/O
card read. In the case of a memory card read, the address hold delay time from the data sampling
timing is set. The setting of these bits is selected when the PCMCIA interface access TC bit is 0.
Bit 5: A5TEH2
0
1
Bit 4: A5TEH1
0
1
0
1
Bit 3: A5TEH0
0
1
0
1
0
1
0
1
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
Rev.4.00 Oct. 10, 2008 Page 385 of 1122
REJ09B0370-0400