SH7751 Datasheet, PDF (521/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
CKIO
Address
CSn
RD/WR
Tnop Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tce
c1
c2
c8
End of RAS down mode
RAS
CASn
D31–D0
(read)
BS
DACKn
(SA: IO ← memory)
d1
d2
d8
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.19 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(EDO Mode, RCD = 0, AnW = 0)
Rev.4.00 Oct. 10, 2008 Page 423 of 1122
REJ09B0370-0400