SH7751 Datasheet, PDF (168/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

3. Memory Management Unit (MMU)
Ensure that values for which “Setting prohibited” is indicated in the above table are not set at
the discretion of software. After a power-on or manual reset the LRUI bits are initialized to 0,
and therefore a prohibited setting is never made by a hardware update.
• URB: Bits that indicate the UTLB entry boundary at which replacement is to be performed.
Valid only when URB > 0.
• URC: Random counter for indicating the UTLB entry for which replacement is to be
performed with an LDTLB instruction. URC is incremented each time the UTLB is accessed.
When URB > 0, URC is reset to 0 when the condition URC = URB occurs. Also note that, if a
value is written to URC by software which results in the condition URC > URB, incrementing
is first performed in excess of URB until URC = H'3F. URC is not incremented by an LDTLB
instruction.
• SQMD: Store queue mode bit. Specifies the right of access to the store queues.
0: User/privileged access possible
1: Privileged access possible (address error exception in case of user access)
• SV: Bit that switches between single virtual memory mode and multiple virtual memory mode.
0: Multiple virtual memory mode
1: Single virtual memory mode
When this bit is changed, ensure that 1 is also written to the TI bit.
• TI: TLB invalidation bit. Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB
bits. This bit always returns 0 when read.
• AT: Address translation enable bit. Specifies MMU enabling or disabling.
0: MMU disabled
1: MMU enabled
MMU exceptions are not generated when the AT bit is 0. In the case of software that does not
use the MMU, therefore, the AT bit should be cleared to 0.
Rev.4.00 Oct. 10, 2008 Page 70 of 1122
REJ09B0370-0400