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SH7751 Datasheet, PDF (994/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer
22. PCI Controller (PCIC)
Bits 31 to 16—Reserved: These bits always return 0 when read. Always write 0 to these bits.
Bit 15—Unlocked Transfer Detection Interrupt Mask (M_LOCKON)
Bit 14—Target Target Abort Interrupt Mask (T_TGT_ABORT)
Bits 13 to 10—Reserved: These bits always return 0 when read. Always write 0 to these bits.
Bit 9—Target Retry Timeout Interrupt Mask (TGT_RETRY)
Bit 8—Master Function Disable Error Interrupt Mask (MST_DIS)
Bit 7—Address Parity Error Detection Interrupt Mask (ADRPERR)
Bit 6—SERR Detection Interrupt Mask (SERR_DET)
Bit 5—Target Write Data Parity Error Interrupt Mask (T_DPERR_WT)
Bit 4—Target Read PERR Detection Interrupt Mask (T_PERR_DET)
Bit 3—Master Target Abort Interrupt Mask (M_TGT_ABORT)
Bit 2—Master Master Abort Interrupt Mask (M_MST_ABORT)
Bit 1—Master Write Data Parity Error Interrupt Mask (M_DPERR_WT)
Bit 0—Master Read Data Parity Error Interrupt Mask (M_DPERR_RD)
Rev.4.00 Oct. 10, 2008 Page 896 of 1122
REJ09B0370-0400