SH7751 Datasheet, PDF (1076/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
1. If the problem concerns target latency, clear to 0 bit 12 (target bus timeout interrupt mask) in
the PCI arbiter interrupt mask register (PCIAINTM) to mask the target bus timeout interrupt.
2. If the problem concerns master data latency, clear to 0 bit 11 (master bus timeout interrupt
mask) in the PCI arbiter interrupt mask register (PCIAINTM) to mask the master bus timeout
interrupt.
Note that if the above interrupts are masked, no interrupt will occur when the 16-clock rule or
8-clock rule of PCI 2.1 specification is violated, even if the violation is detected.
PCICLK
AD[31:0]
C/BE[3:0]
FRAME
IRDY
DEVSEL
TRDY
STOP
01234
11 12 13 14 15 16
A
C
PCIAINT: Bit 12 asserted
Figure 22.24 Target Bus Timeout Interrupt Generation Example 1
(Example in which the Target Device Asserts STOP at the Sixteenth Clock Cycle after
FRAME Was Asserted)
Rev.4.00 Oct. 10, 2008 Page 978 of 1122
REJ09B0370-0400