SH7751 Datasheet, PDF (997/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
A valid value is retained only when one of the PCIINT register bits is set to 1.
The error source holding circuit can only store one error source. For this reason, any second or
subsequent error factors are not stored if errors occur consecutively.
Bit 31—PIO Error (MSTPIO): Error occurred in PIO transfer.
Bit 30—DMA0 Error (MSTDMA0): Error occurred in DMA channel 0 transfer.
Bit 29—DMA1 Error (MSTDMA1): Error occurred in DMA channel 1 transfer.
Bit 28—DMA2 Error (MSTDMA2): Error occurred in DMA channel 2 transfer.
Bit 27—DMA3 Error (MSTDMA3): Error occurred in DMA channel 3 transfer.
Bit 26—Target Error (TGT): Error occurred in target read or target write transfer.
Bits 25 to 4—Reserved: These bits are always read as 0.
Bits 3 to 0—Command Log (CMDLOG3 to 0): These bits retain the PCI transfer command
information (value of C/BE line) upon detection of an error. (Initial value is undefined.)
Rev.4.00 Oct. 10, 2008 Page 899 of 1122
REJ09B0370-0400