SH7751 Datasheet, PDF (347/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. Power-Down Modes
Note: * Terminate DMA transfers prior to making the transition to deep sleep mode. If you
make a transition to deep sleep mode while DMA transfers are in progress, the results
of those transfers cannot be guaranteed.
9.4.2 Exit from Deep Sleep Mode
As with sleep mode, deep sleep mode is exited by means of an interrupt (NMI, IRL, or on-chip
peripheral module) or a reset.
9.5 Pin Sleep Mode
9.5.1 Transition to Pin Sleep Mode
Changing the SLEEP pin to the low level causes this LSI to make a transition to sleep mode.
To ensure that memory is correctly refreshed, use this function when the DSLP bit of STBCR2 is
set to 0.
9.5.2 Exit from Pin Sleep Mode
Setting the SLEEP pin level high causes this LSI to return to the normal state. The pin sleep mode
is also canceled when the conditions specified in section 9.3.2, “Exit From Sleep Mode” are
satisfied.
In a power-on reset, the SLEEP pin should be fixed high.
9.6 Standby Mode
9.6.1 Transition to Standby Mode
If a SLEEP instruction is executed when the STBY bit in STBCR is set to 1, the chip switches
from the program execution state to standby mode. In standby mode, the on-chip peripheral
modules halt as well as the CPU. Clock output from the CKIO pin is also stopped.
The CPU and cache register contents are retained. Some on-chip peripheral module registers are
initialized. The state of the peripheral module registers in standby mode is shown in table 9.4.
Rev.4.00 Oct. 10, 2008 Page 249 of 1122
REJ09B0370-0400