SH7751 Datasheet, PDF (204/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
Figure 4.2 shows the configuration of the operand cache in the SH7751.
Figure 4.3 shows the configuration of the operand cache in the SH7751R.
Effective address
31
26 25
13 12 11 10 9
543 21 0
OIX
22
[13]
9
0
RAM area
determination
ORA
[12]
[11:5]
Address array
3
Tag
UV
Longword (LW) selection
Data array
LW0 LW1 LW2 LW3 LW4 LW5 LW6 LW7
MMU
19
511 19 bits 1 bit 1 bit
32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits 32 bits
Compare
Read data
Write data
Hit signal
Figure 4.2 Configuration of Operand Cache (SH7751)
Rev.4.00 Oct. 10, 2008 Page 106 of 1122
REJ09B0370-0400