SH7751 Datasheet, PDF (81/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 14.27 Single Address Mode/External Device → Synchronous DRAM Longword
Transfer SDRAM Auto-Precharge Write Bus Cycle, Burst
(RCD = 1, TRWL = 2, TPC=1).............................................................................. 560
Figure 14.28 Dual Address Mode/Synchronous DRAM → SRAM Longword Transfer ............ 561
Figure 14.29 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer ........................................... 562
Figure 14.30 Single Address Mode/Burst Mode/External Device → External Bus 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer ........................................... 562
Figure 14.31 Single Address Mode/Burst Mode/External Bus → External Device 32-Bit
Transfer/Channel 0 On-Demand Data Transfer ..................................................... 563
Figure 14.32 Single Address Mode/Burst Mode/External Device → External Bus 32-Bit
Transfer/Channel 0 On-Demand Data Transfer ..................................................... 564
Figure 14.33 Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) ..... 565
Figure 14.34 Handshake Protocol without Use of Data Bus
(Channel 0 On-Demand Data Transfer) ................................................................. 566
Figure 14.35 Read from Synchronous DRAM Precharge Bank .................................................. 567
Figure 14.36 Read from Synchronous DRAM Non-Precharge Bank (Row Miss) ...................... 567
Figure 14.37 Read from Synchronous DRAM (Row Hit) ........................................................... 568
Figure 14.38 Write to Synchronous DRAM Precharge Bank...................................................... 568
Figure 14.39 Write to Synchronous DRAM Non-Precharge Bank (Row Miss).......................... 569
Figure 14.40 Write to Synchronous DRAM (Row Hit)............................................................... 569
Figure 14.41 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Block Transfer/Channel 0 On-Demand Data Transfer ........................................... 570
Figure 14.42 DDT Mode Setting ................................................................................................. 571
Figure 14.43 Single Address Mode/Burst Mode/Edge Detection/ External Device
→ External Bus Data Transfer ............................................................................... 571
Figure 14.44 Single Address Mode/Burst Mode/Level Detection/ External Bus
→ External Device Data Transfer .......................................................................... 572
Figure 14.45 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Bus → External Device Data Transfer................................... 572
Figure 14.46 Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Device → External Bus Data Transfer................................... 573
Figure 14.47 Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer
Request to Channels 1–3 Using Data Bus .............................................................. 574
Figure 14.48 Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus
→ External Device Data Transfer/ Direct Data Transfer Request to Channel 2
without Using Data Bus ......................................................................................... 575
Figure 14.49 Single Address Mode/Burst Mode/External Bus → External Device Data
Transfer/Direct Data Transfer Request to Channel 2 ............................................. 576
Rev.4.00 Oct. 10, 2008 Page lxxxi of xcviii
REJ09B0370-0400