SH7751 Datasheet, PDF (228/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
1. OC data array read
Longword data is read into the data field from the data specified by the longword specification
bits in the address field in the OC entry corresponding to the way and entry set in the address
field.
2. OC data array write
The longword data specified in the data field is written for the data specified by the longword
specification bits in the address field in the OC entry corresponding to the way and entry set in
the address field. This write does not set the U bit to 1 on the address array side.
31
24 23
Address field _{1 1 1 1 0 1 0 1}
31
Data field
15 1413
Way
Longword data
Entry
54 210
L
0
Legend:
L: Longword specification bits
: Reserved bits (0 write value, undefined read value)
Figure 4.15 Memory-Mapped OC Data Array
4.6.5 Summary of Memory-Mapped OC Addresses
The memory-mapped OC addresses in cache-double-mode in the SH7751R are summarized below
using data area access as an example.
• Normal mode (CCR.ORA = 0)
H'F500 0000 to H'F500 3FFF (16 KB): Way 0 (entries 0 to 511)
H'F500 4000 to H'F500 7FFF (16 KB): Way 1 (entries 0 to 511)
:
:
:
A shadow of the cache area occurs every 32 Kbytes up to H'F5FF FFFF.
• RAM mode (CCR.ORA = 1)
H'F500 0000 to H'F500 1FFF (8 KB): Way 0 (entries 0 to 255)
H'F500 2000 to H'F500 3FFF (8 KB): Way 1 (entries 0 to 255)
:
:
:
A shadow of the cache area occurs every 16 Kbytes up to H'F5FF FFFF.
Rev.4.00 Oct. 10, 2008 Page 130 of 1122
REJ09B0370-0400