SH7751 Datasheet, PDF (235/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 5 Exceptions
5. Exceptions
5.1 Overview
5.1.1 Features
Exception handling is processing handled by a special routine, separate from normal program
processing, that is executed by the CPU in case of abnormal events. For example, if the executing
instruction ends abnormally, appropriate action must be taken in order to return to the original
program sequence, or report the abnormality before terminating the processing. The process of
generating an exception handling request in response to abnormal termination, and passing control
flow to an exception handling routine, etc., is given the generic name of exception handling.
SH-4 exception handling is of three kinds: for resets, general exceptions, and interrupts.
5.1.2 Register Configuration
The registers used in exception handling are shown in table 5.1.
Table 5.1 Exception-Related Registers
Name
Abbrevia-
tion
R/W
Initial Value
P4
Address*²
Area 7
Address*²
Access
Size
TRAPA exception TRA
register
R/W Undefined
H'FF00 0020 H'1F00 0020 32
Exception event
register
EXPEVT R/W
H'0000 0000/ H'FF00 0024 H'1F00 0024 32
H'0000 0020*¹
Interrupt event
register
INTEVT R/W Undefined
H'FF00 0028 H'1F00 0028 32
Notes: 1. H'0000 0000 is set in a power-on reset, and H'0000 0020 in a manual reset.
2. P4 address is the address when using the virtual/physical address space P4 area.
When making an access from area 7 in the physical address space using the TLB, the
three high most bits of the address are ignored.
Rev.4.00 Oct. 10, 2008 Page 137 of 1122
REJ09B0370-0400