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SH7751 Datasheet, PDF (607/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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14. Direct Memory Access Controller (DMAC)
Bits 27 to 25âDestination Address Space Attribute Specification (DSA2âDSA0): These bits
specify the space attribute for PCMCIA interface area access.
Bit 27: DSA2 Bit 26: DSA1 Bit 25: DSA0 Description
0
0
0
Reserved in PCMCIA access
1
Dynamic bus sizing I/O space
1
0
8-bit I/O space
1
16-bit I/O space
1
0
0
8-bit common memory space
1
16-bit common memory space
1
0
8-bit attribute memory space
1
16-bit attribute memory space
(Initial value)
Bit 24âDestination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait
cycle control for PCMCIA interface area access. This bit selects the wait control register in the
BSC that performs area 5 and 6 wait cycle control.
Bit 24: DTC
Description
0
CS5 space wait cycle selection
(Initial value)
Settings of bits A5W2âA5W0 in wait control register 2 (WCR2), and bits
A5PCW1âA5PCW0, A5TED2âA5TED0, and A5TEH2âA5TEH0 in the
PCMCIA control register (PCR), are selected
1
CS6 space wait cycle selection
Settings of bits A6W2âA6W0 in wait control register 2 (WCR2), and bits
A6PCW1âA6PCW0, A6TED2âA6TED0, and A6TEH2âA6TEH0 in the
PCMCIA control register (PCR), are selected
Note: For details, see section 13.3.7, PCMCIA Interface.
Bits 23 to 20âReserved: These bits are always read as 0, and should only be written with 0.
Rev.4.00 Oct. 10, 2008 Page 509 of 1122
REJ09B0370-0400
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