SH7751 Datasheet, PDF (1064/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
22.4.5 Endian Control in Target Transfers (I/O Read/I/O Write)
The access size is fixed at longword when accessing the PCIC local register using I/O read or I/O
write commands. Addresses are specified using 4-byte boundaries, and BE[3:0] is specified as
B'0000.
The data alignment in target transfers (I/O read and I/O write) is shown in figure 22.22.
Target I/O read transfer data alignment (local register PCI bus)
Size
Address
LW
4n
Local register
31
0
B3 B2 B1 B0
PCI bus
31
0
B3 B2 B1 B0
BE
H'0000
Target I/O write transfer data alignment (PCI bus local register)
Size
Address
LW
4n
Local register
31
0
B3 B2 B1 B0
PCI bus
31
0
B3 B2 B1 B0
BE
H'0000
Figure 22.22 Data Alignment at Target I/O Transfer (Both Big Endian and Little Endian)
22.4.6 Endian Control in Target Transfers (Configuration Read/Configuration Write)
The data alignment when accessing the PCIC configuration register using the target configuration
read and configuration write commands is shown in figure 22.23.
In the SH7751 the access size is fixed at longword. The BE[3:0] value is ignored. In the SH7751R
all BE combinations are valid.
Rev.4.00 Oct. 10, 2008 Page 966 of 1122
REJ09B0370-0400