SH7751 Datasheet, PDF (993/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22.2.21 PCI Interrupt Mask Register (PCIINTM)
Bit: 31
30
29
28
27
—
—
—
—
—
Initial value:
0
0
0
0
0
PCI-R/W: R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
22. PCI Controller (PCIC)
26
25
24
—
—
—
0
0
0
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
—
—
—
—
—
—
—
—
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R
R
R
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
M_LOCK T_TGT_A —
—
—
— TGT_RET MST_DIS
ON BORT
RY
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: R/W
R/W
R
R
R
R
R/W
R/W
PP Bus-R/W: R/W
R/W
R
R
R
R
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
ADRPER SERR_D T_DPER T_PERR_ M_TGT_A M_MST_ M_DPER M_DPER
R
ET
R_WT DET BORT ABORT R_WT R_RD
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The PCI interrupt mask register (PCIINTM) sets the respective interrupt masks for the interrupts
generated when errors occur in PCI transfers. It is a 32-bit read/write register that can be accessed
from both the PP bus and PCI bus. When set to 0, the respective interrupt is disabled, and enabled
when set to 1.
The PCIINTM register is initialized to H'00000000 at a power-on reset and software reset.
Rev.4.00 Oct. 10, 2008 Page 895 of 1122
REJ09B0370-0400