SH7751 Datasheet, PDF (480/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
• For Synchronous DRAM Interface:
AMX
AMXEXT SZ
Example Synchronous DRAM
Configurations
0
0
32
(16M: 512K × 16 bits × 2) × 2
1
(16M: 512K × 16 bits × 2) × 2
1
0
(16M: 1M × 8 bits × 2) × 4
1
(16M: 1M × 8 bits × 2) × 4
2
—
(64M: 1M × 16 bits × 4) × 2
3
—
(64M: 2M × 8 bits × 4) × 4
4
—
(64M: 512K × 32 bits × 4) × 1
5
—
(64M: 1M × 32 bits × 2) × 1
6
0
(64M: 4M × 4 bits × 4) × 8
1
(256M: 4M × 16 bits × 4) × 2
7
—
(16M: 256K × 32 bits × 2) × 1
Note: * a[x]: External address, not address pin
BANK
a[21]*
a[20]*
a[22]*
a[21]*
a[23:22]*
a[24:23]*
a[22:21]*
a[22]*
a[25:24]*
a[25:24]*
a[20]*
Bit 2—Refresh Control (RFSH): Specifies refresh control. Selects whether refreshing is
performed for DRAM and synchronous DRAM. When the refresh function is not used, the refresh
request cycle generation timer can be used as an interval timer.
Bit 2: RFSH
0
1
Description
Refreshing is not performed
Refreshing is performed
(Initial value)
Rev.4.00 Oct. 10, 2008 Page 382 of 1122
REJ09B0370-0400