SH7751 Datasheet, PDF (628/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
CKIO
A28–A0
CSn
D63–D0
RD
WE
DACK
Transfer source
address
Data read cycle
(1st cycle)
Transfer destination
address
Data write cycle
(2nd cycle)
Transfer from external memory space to external memory space
Figure 14.8 Example of Transfer Timing in Dual Address Mode
Bus Modes
There are two bus modes, cycle steal mode and burst mode, selected with the TM bit in CHCR0–
CHCR3.
Cycle Steal Mode: In cycle steal mode, the DMAC releases the bus to the CPU at the end of each
transfer-unit (8-bit, 16-bit, 32-bit, 64-bit, or 32-byte) transfer. When the next transfer request is
issued, the DMAC reacquires the bus from the CPU and carries out another transfer-unit transfer.
At the end of this transfer, the bus is again given to the CPU. This is repeated until the transfer end
condition is satisfied.
Cycle steal mode can be used with all categories of transfer request source, transfer source, and
transfer destination.
Figure 14.9 shows an example of DMA transfer timing in cycle steal mode. The transfer
conditions in this example are dual address mode and DREQ level detection.
Rev.4.00 Oct. 10, 2008 Page 530 of 1122
REJ09B0370-0400