SH7751 Datasheet, PDF (1008/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
22.2.31 PCI DMA Control Register [3:0] (PCIDCR [3:0])
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value:
0
0
0
...
0
0
0
0
PCI-R/W: R
R
R
...
R
R
R
R
PP Bus-R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
— ALNMD10 ALMMD9 DMAST
Initial value:
0
0
0
0
0
0
0
0
PCI-R/W: R
R
R
R
R
R/W
R/W
R
PP Bus-R/W: R
R
R
R
R
R/W
R/W
R
Bit:
7
6
5
4
DMAIM DMAIS LAHOLD
—
Initial value:
0
0
0
0
PCI-R/W: R/W R/WC R/W
R
PP Bus-R/W: R/W R/WC R/W
R
3
IOSEL0
0
R/W
R/W
Note: Cleared by writing WC:1. (Writing of 0 is ignored.)
2
DIR
0
R/W
R/W
1
0
DMASTOP DMASTRT
0
0
R/W
R/W
R/W
R/W
The DMA transfer control register [3:0] (PCIDCR [3:0]) specifies the operating mode of the
respective channels and the method of transfer, etc. This 32-bit read/write register can be accessed
from the PP bus and PCI bus.
The PCIDCR register is initialized to H'00000000 at a power-on reset and software reset.
Writing 1 to bit 0 (DMASTRT) starts DMA transfer. Always re-set the value in this register before
starting a new DMA transfer after completion of a DMA transfer.
When setting the DMASTOP bit, do not write 1 to the DMASTART bit. Also, write the same
setting at the start of transfer to the DMAIM, DMAIS, LAHOLD, IOSEL and DIR bits.
Example: Starting transfer with PCIDCR = H'00000085
Forced DMA termination PCIDCR = H'00000086
If DMA is forcibly terminated with a value other than the setting used in the transfer being
performed, data accuracy is not guaranteed.
Rev.4.00 Oct. 10, 2008 Page 910 of 1122
REJ09B0370-0400