SH7751 Datasheet, PDF (970/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
20) of the address used when a device on the PCI bus accesses local memory on the SH local bus
using memory transfer commands. Minimally, allocate the capacity set in the local space register 1
(PCILSR1) to PCI bus memory space.
Bits 19 to 0 are fixed in hardware. The number of valid bits of those that can be written to (bit 31
to 20) differs according to the value set in PCILSR1.
Table 22.7 Memory Space Base Address Register (BASE1)
PCILSR1 [28:20]
Register Value
B'0_0000_0000
B'0_0000_0001
B'0_0000_0011
:
B'0_1111_1111
B'1_1111_1111
Required Address
Space
1 MB
2 MB
4 MB
:
256 MB
512 MB
Valid BASE1 [31:20]
Write Bits
Bits 31 to 20
Bits 31 to 21
Bits 31 to 22
:
Bits 31 to 28
Bits 31 to 29
The PCICONF6 register is initialized to H'00000000 at a power-on reset and software reset.
Always write to this register prior to transferring data to or from the PCIC memory from the PCI
bus.
Bits 31 to 20—Base Address of the Memory Space 1 (BASE1 31 to 20): Specifies the base
address of the local address space 1 (this LSI external bus space).
Bits 19 to 4—Base Address of the Memory Space 1 (BASE1 19 to 4): Fixed at H'0000 in
hardware.
Bit 3—Pre-fetch Control (LA1PREF): Shows whether the local address space 1 can be pre-
fetched.
Bit 3: LA1PREF
0
1
Description
Prefetch disabled
Prefetch enabled (not supported)
(Initial value)
Rev.4.00 Oct. 10, 2008 Page 872 of 1122
REJ09B0370-0400