SH7751 Datasheet, PDF (59/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4.3.8 Coherency between Cache and External Memory ............................................... 113
4.3.9 Prefetch Operation ............................................................................................... 113
4.3.10 Notes on Using OC RAM Mode (SH7751R Only) when in Cache Enhanced
Mode .................................................................................................................... 114
4.4 Instruction Cache (IC)....................................................................................................... 116
4.4.1 Configuration ....................................................................................................... 116
4.4.2 Read Operation .................................................................................................... 119
4.4.3 IC Index Mode ..................................................................................................... 120
4.5 Memory-Mapped Cache Configuration (SH7751)............................................................ 120
4.5.1 IC Address Array ................................................................................................. 120
4.5.2 IC Data Array....................................................................................................... 122
4.5.3 OC Address Array................................................................................................ 123
4.5.4 OC Data Array ..................................................................................................... 124
4.6 Memory-Mapped Cache Configuration (SH7751R) ......................................................... 125
4.6.1 IC Address Array ................................................................................................. 125
4.6.2 IC Data Array....................................................................................................... 127
4.6.3 OC Address Array................................................................................................ 128
4.6.4 OC Data Array ..................................................................................................... 129
4.6.5 Summary of Memory-Mapped OC Addresses..................................................... 130
4.7 Store Queues ..................................................................................................................... 131
4.7.1 SQ Configuration ................................................................................................. 131
4.7.2 SQ Writes............................................................................................................. 131
4.7.3 Transfer to External Memory............................................................................... 132
4.7.4 Determination of SQ Access Exception............................................................... 133
4.7.5 SQ Read (SH7751R only).................................................................................... 133
4.7.6 SQ Usage Notes (SH7751 Only).......................................................................... 134
Section 5 Exceptions........................................................................................................... 137
5.1 Overview........................................................................................................................... 137
5.1.1 Features................................................................................................................ 137
5.1.2 Register Configuration......................................................................................... 137
5.2 Register Descriptions ........................................................................................................ 138
5.3 Exception Handling Functions .......................................................................................... 139
5.3.1 Exception Handling Flow .................................................................................... 139
5.3.2 Exception Handling Vector Addresses ................................................................ 139
5.4 Exception Types and Priorities ......................................................................................... 140
5.5 Exception Flow ................................................................................................................. 143
5.5.1 Exception Flow .................................................................................................... 143
5.5.2 Exception Source Acceptance.............................................................................. 144
5.5.3 Exception Requests and BL Bit ........................................................................... 146
Rev.4.00 Oct. 10, 2008 Page lix of xcviii
REJ09B0370-0400