SH7751 Datasheet, PDF (47/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
23.3.1 Clock and
996
Control Signal Timing
Table 23.14 Clock and
Control Signal Timing
(HD6417751RBP240
(V), HD6417751RBG240
(V))
Table 23.15 Clock and 997
Control Signal Timing
(HD6417751RF240 (V))
Table 23.16 Clock and 998
Control Signal Timing
(HD6417751RBP200
(V), HD6417751RBG200
(V))
Table 23.17 Clock and 999
Control Signal Timing
(HD6417751RF200 (V))
Table 23.18 Clock and 1000
Control Signal Timing
(HD6417751BP167 (V),
HD6417751F167 (V) )
Table 23.23 Clock and ⎯
Control Signal Timing
(HD6417751VF133)
23.3.2 Control Signal 1006
Timing
Table 23.19 Control
Signal Timing
Revision (See Manual for Details)
Title and description amended
V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, T_a = –20 to 75°C, C_L = 30 pF
Table amended
V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, T_a = –20 to 75°C, C_L = 30 pF
Item
Symbol Min
Max
Unit Figure
CKIO clock
output
PLL1/PLL2 operating
PLL1/PLL2 not operating
f_OP
25
84
MHz
1
34
MHz
Title and description amended
V = 3.0 to 3.6 V, V = 1.5 V, T = –20 to 75°C, C = 30 pF
DDQ
DD
a
L
Description amended
V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, T_a = –20 to 75°C, C_L = 30 pF
Title and description amended
V = 3.0 to 3.6 V, V = 1.8 V, T = –20 to 75°C, C = 30 pF
DDQ
DD
a
L
Table deleted
Table amended
Item
Symbol
HD6417751R
BP240 (V)
HD6417751R
BG240 (V)
HD6417751R
BP200 (V)
HD6417751R
BG200 (V)
HD6417751R
F240 (V)
HD6417751R
F200 (V)
*
*
*
*
Min Max Min Max Min Max Min Max Unit
Figure
Bus tri-state delay
time to standby
mode
t_BOFF2
Bus buffer on time t_BON1
Bus buffer on time t_BON2
from standby
STATUS 0/1 delay t_STD1
time to
t_STD2
t_STD3
—2
—2
—2
—2
t_cyc
23.12 (2)
— 12
—2
—6
—2
—2
— 12
—2
—6
—2
—2
— 12
—2
—6
—2
—2
— 12 ns 23.11
—2
t_cyc
23.12 (2)
—6
—2
—2
ns 23.12 (1)
t_cyc
23.12
(1) (2)
t_cyc
23.12 (2)
Rev.4.00 Oct. 10, 2008 Page xlvii of xcviii
REJ09B0370-0400