SH7751 Datasheet, PDF (983/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
The PCICR register is initialized at a power-on reset to H'000000*0 (bits 7 and 6 are initialized to
B'00, and bits 5 and 4 sample the value of mode pins 9 and 10). At a software reset, bit 1
(RSTCTL) is not initialized. All other bits are initialized in the same way as at a software reset.
This register can be written to only when bits 31 to 24 are H'A5.
Always set bit 0 (CFINIT) to 1 on completion of PCIC register initialization.
Bits 31 to 10—Reserved: These bits are always read as 0. When writing, write H'A5 to bits 31 to
24, and 0 to others.
Bit 9—Target Read Single Buffer (TRDSGL): This bit specifies whether one target read buffer
(32 bytes) or two target read buffers (64 bytes) are used for target memory read access to the
PCIC. When two target read buffers faces are used, the data from two buffers are read via the local
bus in advanced.
Bit 9: TRDSGL
0
1
Description
Use 2 target read buffers
Use 1 target read buffer only
(Initial value)
Bit 8—Data Byte Swap (BYTESWAP): Specifies whether the data byte is swapped when the
PCIC performs PIO transfer.
Bit 8: BYTESWAP Description
0
Send data as-is
1
Swap data byte before sending
Note: For details, refer to section 22.4, Endians.
(Initial value)
Bit 7—PCI Signal Pull-up (PCIUP): Controls the pull-up resistance of the PCI signal. Regarding
the pins that are subject to pull-up, refer to table 22.1. Regarding the pull-up control provided
when the PCIPEQ2/MD9, PCIREQ3/MD10 or PCIREQ4 is used as a port, refer to the section on
port control register (PCIPCTR).
Bit 7: PCIUP
0
1
Description
Pull-up
No pull-up
(Initial value)
Rev.4.00 Oct. 10, 2008 Page 885 of 1122
REJ09B0370-0400