SH7751 Datasheet, PDF (908/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. User Break Controller (UBC)
4. When sequential condition mode has been selected, and the channel B condition is matched
after the channel A condition has been matched, a break is effected at the instruction at which
the channel B condition was matched. See section 20.3.8, Contiguous A and B Settings for
Sequential Conditions, for the operation when the channel A condition match and channel B
condition match occur close together. With sequential conditions, only the channel B condition
match flag is set. When sequential condition mode has been selected, if it is wished to clear the
channel A match when the channel A condition has been matched but the channel B condition
has not yet been matched, this can be done by writing 0 to the SEQ bit in the BRCR register.
20.3.4 Instruction Access Cycle Break
1. When an instruction access/read/word setting is made in the break bus cycle register
(BBRA/BBRB), an instruction access cycle can be used as a break condition. In this case,
breaking before or after execution of the relevant instruction can be selected with the
PCBA/PCBB bit in the break control register (BRCR). When an instruction access cycle is
used as a break condition, clear the LSB of the break address registers (BARA, BARB) to 0. A
break will not be generated if this bit is set to 1.
2. When a pre-execution break is specified, the break is effected when it is confirmed that the
instruction is to be fetched and executed. Therefore, overrun-fetched instructions (instructions
that are fetched but not executed when a branch or exception occurs) cannot be used in a break.
However, if a TLB miss or TLB protection violation exception occurs at the time of the fetch
of instructions subject to a break, the break exception handling is carried out first. The
instruction TLB exception handling is performed when the instruction is re-executed (see
section 5.4, Exception Types and Priorities). Also, since a delayed branch instruction and the
delay slot instruction are executed as a single instruction, if a pre-execution break is specified
for a delay slot instruction, the break will be effected before execution of the delayed branch
instruction. However, a pre-execution break cannot be specified for the delay slot instruction
for an RTE instruction.
3. With a post-execution break, the instruction set as a break condition is executed, then a break
interrupt is generated before the next instruction is executed. When a post-execution break is
set for a delayed branch instruction, the delay slot is executed and the break is effected before
execution of the instruction at the branch destination (when the branch is made) or the
instruction two instructions ahead of the branch instruction (when the branch is not made).
4. When an instruction access cycle is set for channel B, break data register B (BDRB) is ignored
in judging whether there is an instruction access match. Therefore, a break condition specified
by the DBEB bit in BRCR is not executed.
Rev.4.00 Oct. 10, 2008 Page 810 of 1122
REJ09B0370-0400