SH7751 Datasheet, PDF (534/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
Tr Trw Tc1 Tc2 Tc3 Tc4 Trwl Trwl Tpc
Row
Row
H/L
Row
c1
CASS
DQMn
D31–D0
c1
(write)
BS
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.27 Basic Timing for Synchronous DRAM Single Write
Rev.4.00 Oct. 10, 2008 Page 436 of 1122
REJ09B0370-0400