SH7751 Datasheet, PDF (692/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
Table 14.15 Channel Selection by DTR Format (DMAOR.DBL = 1)
DTR.ID[1:0]
00
01
10
11
DTR.SZ[2:0] ≠ 101
CH0
CH1
CH2
CH3
DTR.SZ[2:0] = 101
CH4
CH5
CH6
CH7
31 29 28 27 26 25 24 23
16
0
SZ
ID MD COUNT^*
(Reserved)
Reserved
Note: * These bits are valid when request queue clear is specified (with no transfer count function).
Figure 14.54 DTR Format (Transfer Request Format) (SH7751R)
Bits 13 to 10—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for
channel execution when transfer requests are made for a number of channels simultaneously.
DMAOR
Bit 9
PR1
0
0
1
1
DMAOR
Bit 8
PR0
0
1
0
1
Description
CH0 > CH1 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7
CH0 > CH2 > CH3 > CH4 > CH5 > CH6 > CH7 > CH1
CH2 > CH0 > CH1 > CH3 > CH4 > CH5 > CH6 > CH7
Round robin mode
(Initial value)
Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an
interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be
cleared by writing 0 after reading 1. For details of the settings, see the description of the AE bit in
section 14.2.5, DMA Operation Register (DMAOR).
Rev.4.00 Oct. 10, 2008 Page 594 of 1122
REJ09B0370-0400