SH7751 Datasheet, PDF (882/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Interrupt Controller (INTC)
As shown in table 19.6, 8 combinations of internal peripheral modules are assigned to one register.
Values of H'F (1111) to H'0 (0000) can be set in each 4 bits, allowing the order levels of the
corresponding interrupts to be set. H'F is priority level 15 (highest level) while H'0 is priority level
0 (request mask).
Reserved: These bits are always read as 0, and should only be written with 0.
19.3.4 Interrupt Factor Register 00 (INTREQ00)
The interrupt factor register 00 (INTREQ00) shows which interrupt have been requested of the
INTC. Even when the interrupts are masked with INTPRI00 and INTMSK00, the bits in this
register are not affected. INTREQ00 is a 32-bit read-only register.
Bit: 31
30
29
...
11
10
9
8
...
Initial value:
0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bits 31 to 0—Interrupt Request: These bits indicate the existence of an interrupt request
corresponding to each bit. For the correspondence between bits and interrupt sources, see section
19.3.7, INTREQ00, INTMSK00, and INTMSKCLR00 Bit Allocation.
Bits 31 to 0
0
1
Description
Shows no corresponding interrupt request
Shows existence of corresponding interrupt request
(Initial value)
19.3.5 Interrupt Mask Register 00 (INTMSK00)
The interrupt mask register 00 (INTMSK00) specifies whether or not to mask individual interrupts
each time they are requested. The INTMSK00 register is a 32-bit register. It is initialized to
H'000003FF at a reset. The values are retained in standby mode.
Rev.4.00 Oct. 10, 2008 Page 784 of 1122
REJ09B0370-0400