SH7751 Datasheet, PDF (1211/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

F. Instruction Prefetching and Its Side Effects
Appendix F Instruction Prefetching and Its Side Effects
The SH7751 Group is provided with an internal buffer for holding pre-read instructions, and
always performs pre-reading. Therefore, program code must not be located in the last 20-byte area
of any memory space. If program code is located in these areas, the memory area will be exceeded
and a bus access for instruction pre-reading may be initiated. A case in which this is a problem is
shown below.
Address
H'03FFFFF8
H'03FFFFFA
Area 0 H'03FFFFFC
H'03FFFFFE
Area 1 H'04000000
H'04000002
...
..
ADD R1,R4
JMP @R2
NOP
NOP
PC (program counter)
Instruction prefetch address
Figure F.1 Instruction Prefetch
Figure F.1 presupposes a case in which the instruction (ADD) indicated by the program counter
(PC) and the address H'04000002 instruction prefetch are executed simultaneously. It is also
assumed that the program branches to an area other than area 1 after executing the following JMP
instruction and delay slot instruction.
In this case, the program flow is unpredictable, and a bus access (instruction prefetch) to area 1
may be initiated.
Instruction Prefetch Side Effects
1. It is possible that an external bus access caused by an instruction prefetch may result in
misoperation of an external device, such as a FIFO, connected to the area concerned.
2. If there is no device to reply to an external bus request caused by an instruction prefetch,
hangup will occur.
Remedies
1. These illegal instruction fetches can be avoided by using the MMU.
2. The problem can be avoided by not locating program code in the last 20 bytes of any area.
Rev.4.00 Oct. 10, 2008 Page 1113 of 1122
REJ09B0370-0400