SH7751 Datasheet, PDF (229/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Caches
4.7 Store Queues
Two 32-byte store queues (SQs) are supported to perform high-speed writes to external memory.
When not using the SQs, the low power dissipation power-down modes, in which SQ functions
are stopped, can be used. The queue address control registers (QACR0 and QACR1) cannot be
accessed while SQ functions are stopped. See section 9, Power-Down Modes, for the procedure
for stopping SQ functions. Note that power-down modes (STBCR2.MSTP6 = 1) that stop SQ
functions cannot be used on the SH7751 when using the operand cache for write-back operations.*
Note: * Cases where write-back operations are performed:
• When the operand cache is used in copy-back mode (determined by the CCR.CB
and CCR.WT bits and, if address translation is performed, the WT bit in the page
management information)
• When the memory allocation cache function is used to write to the OC address
array, and an entry is generated when both the V and U bits are set to 1
4.7.1 SQ Configuration
There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 4.16. These two store
queues can be set independently.
SQ0 ^{SQ0[0] SQ0[1] SQ0[2] SQ0[3] SQ0[4] SQ0[5] SQ0[6] SQ0[7]}
SQ1 ^{SQ1[0] SQ1[1] SQ1[2] SQ1[3] SQ1[4] SQ1[5] SQ1[6] SQ1[7]}
4B
4B
4B
4B
4B
4B
4B
4B
Figure 4.16 Store Queue Configuration
4.7.2 SQ Writes
A write to the SQs can be performed using a store instruction on P4 area H'E000 0000 to H'E3FF
FFFC. A longword or quadword access size can be used. The meaning of the address bits is as
follows:
[31:26]:
[25:6]:
[5]:
111000
Don't care
0/1
Store queue specification
Used for external memory transfer/access right
0: SQ0 specification 1: SQ1 specification
Rev.4.00 Oct. 10, 2008 Page 131 of 1122
REJ09B0370-0400