SH7751 Datasheet, PDF (680/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
c. It takes one cycle for DBREQ to be accepted by the DMAC after being asserted by an
external device. If a row address miss occurs at this time in a read or write in the non-
precharged bank during synchronous DRAM access, and BAVL is asserted, the DBREQ
signal asserted by the external device is ignored. Therefore, BAVL is not asserted again
due to this signal.
11. Clearing DDT mode
Check that DMA transfer is not in progress on any channel before setting the DMAOR.DDT
bit. If the DMAOR.DDT setting is changed from 1 to 0 during DMA transfer in DDT mode,
the DMAC will freeze.
This also applies when switching from normal DMA mode (DMAOR.DDT = 0) to DDT
mode.
12. Confirming DMA transfer requests and number of transfers executed
The channel associated with a DMA bus cycle being executed in response to a DMA transfer
request can be confirmed by determining the level of external pins ID1 and ID0 at the rising
edge of the CKIO clock while TDACK is asserted.
(ID = 00: channel 0; ID = 01: channel 1; ID = 10: channel 2; ID = 11: channel 3)
Rev.4.00 Oct. 10, 2008 Page 582 of 1122
REJ09B0370-0400