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SH7751 Datasheet, PDF (770/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer | |||
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16. Serial Communication Interface with FIFO (SCIF)
⢠Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK2 pin
⢠Four interrupt sources
There are four interrupt sourcesâtransmit-FIFO-data-empty, break, receive-FIFO-data-full,
and receive-errorâthat can issue requests independently.
⢠The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA
transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
⢠When not in use, the SCIF can be stopped by halting its clock supply to reduce power
consumption.
⢠Modem control functions (RTS2 and CTS2) are provided.
⢠The amount of data in the transmit/receive FIFO registers, and the number of receive errors in
the receive data in the receive FIFO register, can be ascertained.
⢠A timeout error (DR) can be detected during reception.
Rev.4.00 Oct. 10, 2008 Page 672 of 1122
REJ09B0370-0400
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