SH7751 Datasheet, PDF (36/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
19.1.3 Pin
771
Configuration
Table 19.1 INTC Pins
19.2.1 NMI Interrupt 772
19.2.2 IRL Interrupts 774
19.2.3 On-Chip
775
Peripheral Module
Interrupts
19.2.4 Interrupt
777
Exception Handling and
Priority
Table 19.4 Interrupt
Exception Handling
Sources and Priority
Order
19.4.1 Interrupt
787
Operation Sequence
Revision (See Manual for Details)
Table amended
Pin Name
Nonmaskable interrupt
input pin
Interrupt input pins
Function
Input of nonmaskable interrupt request
signal
Input of interrupt request signals
(maskable by IMASK in SR)
Description amended
NMI interrupt exception handling does not affect the interrupt
mask level bits (IMASK) in the status register (SR).
Description amended
The interrupt mask bits (IMASK) in the status register (SR) are
not affected by IRL interrupt handling.
Description amended
The interrupt mask bits (IMASK) in the status register (SR) are
not affected by on-chip peripheral module interrupt handling.
Table amended
Interrupt Source
INTEVT Interrupt Priority IPR (Bit
Code (Initial Value) Numbers)
PCIC PCISERR
H'A00 15–0 (0)
PCIERR
PCIPWDWN
PCIPWON
PCIDMA0
PCIDMA1
PCIDMA2
PCIDMA3
H'AE0
H'AC0
H'AA0
H'A80
H'A60
H'A40
H'A20
15–0 (0)
INTPRI00
(3–0)
INTPRI00
(7–4)
Priority within
IPR Setting Unit
—
Default
Priority
High
High
Low
Description amended
3. The priority level of the interrupt selected by the interrupt
controller is compared with the interrupt mask bits (IMASK)
in the status register (SR) of the CPU. If the request priority
level is higher that the level in bits IMASK, the interrupt
controller accepts the interrupt and sends an interrupt
request signal to the CPU.
Notes: 1. The interrupt mask bits (IMASK) in the status
register (SR) are not changed by acceptance of an
interrupt in this LSI.
Rev.4.00 Oct. 10, 2008 Page xxxvi of xcviii
REJ09B0370-0400