SH7751 Datasheet, PDF (528/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
the READA command inside the synchronous DRAM; no new access command can be issued to
the same bank during this cycle. In this LSI, the number of Tpc cycles is determined by the
specification of bits TPC2–TPC0 in MCR, and commands are not issued for the synchronous
DRAM during this interval.
The example in figure 13.24 shows the basic cycle. To connect slower synchronous DRAM, the
cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV
command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by bits
RCD1 and RCD0 in MCR, with a value of 0 to 3 specifying 2 to 4 cycles, respectively. In the case
of 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous
DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READ
command output cycle Tc1 to the first read data latch cycle, Td1, can be specified as 1 to 5 cycles
independently for areas 2 and 3 by means of bits A2W2–A2W0 and A3W2–A3W0 in WCR2. This
number of cycles corresponds to the number of synchronous DRAM CAS latency cycles.
Rev.4.00 Oct. 10, 2008 Page 430 of 1122
REJ09B0370-0400