SH7751 Datasheet, PDF (827/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

17. Smart Card Interface
If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level)
to request retransmission of the data. After outputting the error signal for the prescribed length
of time, the receiving station places the signal line in the high-impedance state again. The
signal line is pulled high again by a pull-up resistor.
5. If the transmitting station does not receive an error signal, it proceeds to transmit the next data
frame.
If it receives an error signal, however, it returns to step 2 and retransmits the erroneous data.
17.3.4 Register Settings
Table 17.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or
1 must be set to the value shown. The setting of other bits is described below.
Table 17.3 Smart Card Interface Register Settings
Register Bit 7
Bit 6
Bit 5
SCSMR1 GM
0
1
SCBRR1 BRR7 BRR6 BRR5
SCSCR1 TIE
RIE
TE
SCTDR1 TDR7 TDR6 TDR5
SCSSR1 TDRE RDRF ORER
SCRDR1 RDR7 RDR6 RDR5
SCSCMR1 —
—
—
SCSPTR1 EIO
—
—
Note: A dash indicates an unused bit.
Bit
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
O/E
1
0
CKS1 CKS0
BRR4 BRR3 BRR2 BRR1 BRR0
RE
0
0
CKE1 CKE0
TDR4 TDR3 TDR2 TDR1 TDR0
FER/ERS PER
TEND 0
0
RDR4 RDR3 RDR2 RDR1 RDR0
—
SDIR SINV —
SMIF
—
SPB1IO SPB1DT SPB0IO SPB0DT
Serial Mode Register (SCSMR1) Settings: The GM bit is used to select the timing of TEND flag
setting, and, together with the CKE1 and CKE0 bits in the serial control register (SCSCR1), to
select the clock output state.
The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the
inverse convention type.
Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section
17.3.5, Clock.
Rev.4.00 Oct. 10, 2008 Page 729 of 1122
REJ09B0370-0400