SH7751 Datasheet, PDF (653/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
14.5.2 Pins in DDT Mode
Figure 14.24 shows the system configuration in DDT mode.
SH7751/SH7751R
DBREQ/DREQ0
BAVL/DRAK0
TR/DREQ1
TDACK/DACK0
ID1, ID0/DRAK1, DACK1
CKIO
D31–D0 = DTR
External device
A25–A0, RAS, CAS, WE, DQMn, CKE
Synchronous
DRAM
Figure 14.24 System Configuration in On-Demand Data Transfer Mode
• DBREQ: Data bus release request signal for transmitting the data transfer request format (DTR
format) or a DMA request from an external device to the DMAC
If there is a wait for release of the data bus, an external device can have the data bus released
by asserting DBREQ. When DBREQ is accepted, the BSC asserts BAVL.
• BAVL: Data bus D31–D0 release signal
Assertion of BAVL means that the data bus will be released two cycles later.
• TR: Transfer request signal
Assertion of TR has the following different meanings.
⎯ In normal data transfer mode (channel 0, except channel 0), TR is asserted, and at the same
time the DTR format is output, two cycles after BAVL is asserted.
⎯ In the case of the handshake protocol without use of the data bus, asserting TR enables a
transfer request to be issued for the channel for which a transfer request was made
immediately before. This function can be used only when BAVL is not asserted two cycles
earlier.
⎯ In the case of direct data transfer mode (valid only for channel 2), a direct transfer request
can be made to channel 2 by asserting DBREQ and TR simultaneously.
Rev.4.00 Oct. 10, 2008 Page 555 of 1122
REJ09B0370-0400