SH7751 Datasheet, PDF (992/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
Bit 3—Master Target Abort Interrupt (M_TGT_ABORT): When the PCIC is master.
Indicates the termination of transaction by target abort.
Bit 2—Master Master Abort Interrupt (M_MST_ABORT): When the PCIC is master.
Indicates the termination of transaction by master abort.
Bit 1—Master Write PERR Detection Interrupt (M_DPERR_WT): When the PCIC is master.
PERR received from the target while writing data to the target. Detects only when bit 6 (PER) of
the PCICONF1 is 1.
Bit 0—Master Read Data Parity Error Interrupt (M_DPERR_RD): When the PCIC is master,
a parity error was detected during a data read from the target. Detects only when bit 6 (PER) of the
PCICONF1 is 1.
Rev.4.00 Oct. 10, 2008 Page 894 of 1122
REJ09B0370-0400