SH7751 Datasheet, PDF (1095/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

23. Electrical Characteristics
Table 23.15 Clock and Control Signal Timing (HD6417751RF240 (V))
V_DDQ = 3.0 to 3.6 V, V_DD = 1.5 V, T_a = –20 to 75°C, C_L = 30 pF
Item
Symbol Min
Max
Unit Figure
EXTAL
PLL1 6-times/PLL2 operation
f_EX
clock input _{PLL1 12-times/PLL2 operation}
frequency
PLL1/PLL2 not operating
16
34
MHz
16
20.0
1
34
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock
output
PLL1/PLL2 operating
PLL1/PLL2 not operating
t_EXcyc
30
1000 ns
23.1
t_EXL
3.5
—
ns
23.1
t_EXH
3.5
—
ns
23.1
t_EXr
—
4
ns
23.1
t_EXf
—
4
ns
23.1
f_OP
25
84
MHz
1
34
MHz
CKIO clock output cycle time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
CKIO clock output rise time
CKIO clock output fall time
CKIO clock output low-level pulse width
CKIO clock output high-level pulse width
Power-on oscillation settling time
Power-on oscillation settling time/mode settling
MD reset setup time
MD reset hold time
RESET assert time
t_cyc
t_CKOL1
t_CKOH1
t_CKOr
t_CKOf
t_CKOL2
t_CKOH2
t_OSC1
t_OSCMD
t_MDRS
t_MDRH
t_RESW
11.9
1000 ns
23.2 (1)
1
—
ns
23.2 (1)
1
—
ns
23.2 (1)
—
3
ns
23.2 (1)
—
3
ns
23.2 (1)
3
—
ns
23.2 (2)
3
—
ns
23.2 (2)
10
—
ms 23.3, 23.5
10
—
ms 23.3, 23.5
3
—
t_cyc
20
—
ns
23.3, 23.5
20
—
t_cyc
23.3, 23.4, 23.5,
23.6
PLL synchronization settling time
t_PLL
200
—
μs
23.9, 23.10
Standby return oscillation settling time 1
t_OSC2
3
—
ms 23.4, 23.6
Standby return oscillation settling time 2
t_OSC3
3
—
ms 23.7
Standby return oscillation settling time 3
t_OSC4
3
—
ms 23.8
Standby return oscillation settling time 1*
t_OSC2
2
—
ms
Standby return oscillation settling time 2*
t_OSC3
2
—
ms
Standby return oscillation settling time 3*
t_OSC4
2
—
ms
IRL interrupt determination time
(RTC used, standby mode)
t_IRLSTB
—
200
μs
23.10
TRST reset hold time
t_TRSTRH
0
—
ns
23.3, 23.5
Notes: When a crystal resonator is connected to EXTAL and XTAL, the maximum frequency is 34 MHz. When
a 3rd overtone crystal resonator is used, an external tank circuit is necessary.
As there is feedback from the CKIO pin when PLL2 is operating, the load capacitance connected to the
CKIO pin should be a maximum of 50 pF.
* When the oscillation settling time of the crystal resonator is 1 ms or less.
Rev.4.00 Oct. 10, 2008 Page 997 of 1122
REJ09B0370-0400