SH7751 Datasheet, PDF (580/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Tm1
Tmd1w Tmd1w
CKIO
Tmd1
Tmd2
RD/FRAME
D31–D0
A
CSn
RD/WR
D0
D1
RDY
BS
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.61 MPX Interface Timing 10
(Burst Read Cycle, AnW = 0, One External Wait Inserted, Bus Width: 32 Bits,
Transfer Data Size: 64 Bits)
Rev.4.00 Oct. 10, 2008 Page 482 of 1122
REJ09B0370-0400