SH7751 Datasheet, PDF (383/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Clock Oscillation Circuits
10.9 Using the WDT
10.9.1 Standby Clearing Procedure
The WDT is used when clearing standby mode by means of an NMI or other interrupt. The
procedure is shown below. (As the WDT does not operate when standby mode is cleared with a
reset, the RESET pin should be held low until the clock stabilizes.)
1. Be sure to clear the TME bit in the WTCSR register to 0 before making a transition to standby
mode. If the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused
when the count overflows.
2. Select the count clock to be used with bits CKS2–CKS0 in the WTCSR register, and set the
initial value in the WTCNT counter. Make these settings so that the time until the count
overflows is at least as long as the clock oscillation stabilization time.
3. Make a transition to standby mode, and stop the clock, by executing a SLEEP instruction.
4. The WDT starts counting on detection of an NMI signal transition edge or an interrupt.
5. When the WDT count overflows, the CPG starts clock supply and the processor resumes
operation. The WOVF flag in the WTCSR register is not set at this time.
6. The counter stops at a value of H'00–H'01. The value at which the counter stops depends on
the clock ratio.
10.9.2 Frequency Changing Procedure
The WDT is used in a frequency change using the PLL. It is not used when the frequency is
changed simply by making a frequency divider switch.
1. Be sure to clear the TME bit in the WTCSR register to 0 before making a frequency change. If
the TME bit is set to 1, an inadvertent reset or interval timer interrupt may be caused when the
count overflows.
2. Select the count clock to be used with bits CKS2–CKS0 in the WTCSR register, and set the
initial value in the WTCNT counter. Make these settings so that the time until the count
overflows is at least as long as the clock oscillation stabilization time.
3. When the frequency control register (FRQCR) is modified, the clock stops. The WDT starts
counting.
4. When the WDT count overflows, the CPG starts clock supply and the processor resumes
operation. The WOVF flag in the WTCSR register is not set at this time.
5. The counter stops at a value of H'00–H'01. The value at which the counter stops depends on
the clock ratio.
Rev.4.00 Oct. 10, 2008 Page 285 of 1122
REJ09B0370-0400