SH7751 Datasheet, PDF (476/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. Bus State Controller (BSC)
Bit 23—CAS Negation Period (TCAS): This bit is valid only when DRAM interface is set.
Bit 23: TCAS
0
1
CAS Negation Period
1
2
(Initial value)
Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): When the DRAM interface is selected,
these bits specify the minimum number of cycles until RAS is asserted again after being negated.
When the synchronous DRAM interface is selected, these bits specify the minimum number of
cycles until the next bank active command after precharging.
Note: For setting values and the period during which no command is issued, see 23.3.3, Bus
Timing.
Bit 21: TPC2
Bit 20: TPC1
Bit 19: TPC0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note: * Inhibited in RAS down mode
RAS Precharge Time
DRAM
Synchronous DRAM
0
1* (Initial value)
1
2
2
3
3
4*
4
5*
5
6*
6
7*
7
8*
Bits 17 and 16—RAS-CAS Delay (RCD1, RCD0): When the DRAM interface is set, these bits
set the RAS-CAS assertion delay time. When the synchronous DRAM interface is set, these bits
set the bank active-read/write command delay time.
Bit 17: RCD1
Bit 16: RCD0
DRAM
0
0
2 cycles
1
3 cycles
1
0
4 cycles
1
5 cycles
Note: * Inhibited in RAS down mode
Description
Synchronous DRAM
Reserved (Setting prohibited)
2 cycles
3 cycles
4 cycles*
Rev.4.00 Oct. 10, 2008 Page 378 of 1122
REJ09B0370-0400