SH7751 Datasheet, PDF (322/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

8. Pipelining
between floating-point registers, FADD is not stalled even if both instructions update the cause
field of FPSCR.
Anti-flow dependency can occur only between a preceding double-precision FADD, FMUL,
FSUB, or FTRV and a following FMOV, FLDI0, FLDI1, FABS, FNEG, or FSTS. See figure 8.3
(g).
If an executing instruction locks any resource—i.e. a function block that performs a basic
operation—a following instruction that attempts to use the locked resource is stalled (figure 8.3
(h)). This kind of stall can be compensated by inserting one or more instructions independent of
the locked resource to separate the interfering instructions. For example, when a load instruction
and an ADD instruction that references the loaded value are consecutive, the 2-cycle stall of the
ADD is eliminated by inserting three instructions without dependency. Software performance can
be improved by such instruction scheduling.
Other causes of a stall are as follows.
• Instruction TLB miss
• Instruction access to external memory (instruction cache miss, etc.)
• Data access to external memory (operand cache miss, etc.)
• Data access to a memory-mapped control register
During the penalty cycles of an instruction TLB miss or external instruction access, no instruction
is issued, but execution of instructions that have already been issued continues. The penalty for a
data access is a pipeline freeze: that is, the execution of uncompleted instructions is interrupted
until the arrival of the requested data. The number of penalty cycles for instruction and data
accesses is largely dependent on the user's memory subsystems.
Rev.4.00 Oct. 10, 2008 Page 224 of 1122
REJ09B0370-0400