SH7751 Datasheet, PDF (353/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9.9.1 In Reset
Power-On Reset
9. Power-Down Modes
CKIO
RESET
PLL stabilization
time
STATUS Normal
Reset
Normal
Manual Reset
0–5 Bcyc
0–30 Bcyc
Figure 9.1 STATUS Output in Power-On Reset
CKIO
RESET (High)
MRESET^*
Must be asserted for
t_RESW or longer
STATUS Normal
Reset
Normal
≥ 0 Bcyc
0–30 Bcyc
Note: * In a manual reset, STATUS = HH (reset) is set and an internal reset started after waiting
until the end of the currently executing bus cycle.
Figure 9.2 STATUS Output in Manual Reset
Rev.4.00 Oct. 10, 2008 Page 255 of 1122
REJ09B0370-0400