SH7751 Datasheet, PDF (22/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Item
Page
13.2.8 Memory Control 377
Register (MCR)
13.2.8 Memory Control 378
Register (MCR)
379
380
13.2.10 Synchronous 387
DRAM Mode Register
(SDMR)
Revision (See Manual for Details)
Description amended of Bit 31
Bit 31—RAS Down (RASD): Sets RAS down mode. When RAS
down mode is used, set BE to 1. Do not set RAS down mode in
slave mode
areas 2 and 3 are both designated as
synchronous DRAM interface.
Table amended of Bit 31
Bit 31: RASD
Description
0
Auto-precharge mode
(Initial value)
1
RAS down mode
Note: When synchronous DRAM is used in RAS down mode, set bits DMAIW2–DMAIW0 to 000
and bits A3IW2–A3IW0 to 000.
Note added, Bits 29 to 27
Note: For setting values and the period during which no
command is issued, see 23.3.3, Bus Timing.
Description and note added, Bits 21 to 19
Bits 21 to 19—RAS Precharge Period (TPC2–TPC0): When the
DRAM interface is selected, these bits specify the minimum
number of cycles until RAS is asserted again after being
negated. When the synchronous DRAM interface is selected,
these bits specify the minimum number of cycles until the next
bank active command after precharging.
Note: For setting values and the period during which no
command is issued, see 23.3.3, Bus Timing.
Description amended of Bits 15 to 13
After a write cycle, the next active command is not issued for a
period set by TPC[2:0] and TRWL[2:0] bits*. …
Note: * For setting values and the period during which no
command is issued, see 23.3.3, Bus Timing.
Description amended of Bits 12 to 10
Bits 12 to 10—CAS-Before-RAS Refresh RAS Assertion Period
(TRAS2–TRAS0): When the DRAM interface is set, these bits
set the RAS assertion period in CAS-before-RAS refreshing.
When the synchronous DRAM interface is set, the bank active
command is not issued for a period set by TPC[2:0] and
TRAS[2:0] bits after an auto-refresh command is issued.
Note: For setting values and the period during which no
command is issued, see 23.3.3, Bus Timing.
Description amended
LMODE: CAS latency
BL:
Burst length
WT:
Wrap type (0: Sequential)
Rev.4.00 Oct. 10, 2008 Page xxii of xcviii
REJ09B0370-0400