SH7751 Datasheet, PDF (1011/1224 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. PCI Controller (PCIC)
22.2.32 PIO Address Register (PCIPAR)
Bit: 31
30
29
28
27
26
25
24
CFGEN
—
—
—
—
—
—
—
Initial value:
1
0
0
0
0
0
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
BUSNO23 BUSNO22 BUSNO21 BUSNO20 BUSNO19 BUSNO18 BUSNO17 BUSNO16
Initial value: —
—
—
—
—
—
—
—
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit: 15
14
13
12
11
10
9
8
DEVNO15 DEVNO14 DEVNO13 DEVNO12 DEVNO11 FNCNO10 FNCNO9 FNCNO8
Initial value: —
—
—
—
—
—
—
—
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
REGADR7 REGADR6 REGADR5 REGADR4 REGADR3 REGADR2 —
—
Initial value: —
—
—
—
—
—
0
0
PCI-R/W: —
—
—
—
—
—
—
—
PP Bus-R/W: R/W
R/W
R/W
R/W
R/W
R/W
R
R
The PIO address register (PCIPAR) is used when issuing configuration cycles on the PCI bus
when the PCIC is host. The PCIC supports the configuration mechanism 1 stipulated in the PCI
local bus specifications. This register is equivalent to the configuration register of configuration
mechanism 1. This register is equivalent to the CONFIG_ADDRESS of configuration mechanism
1. The check that the issuance of the PCI configuration cycle is enabled, and access the PCI
configuration space, this register contains the PCI bus No., device No., Function No., and LW
(longword) boundary of the configuration register. This 32-bit read/write register can be accessed
from the PP bus.
Bit 31 (CFGEN) is set in hardware and none of the other bits of the PCIPAR register are
initialized at a power-on reset or software reset.
Rev.4.00 Oct. 10, 2008 Page 913 of 1122
REJ09B0370-0400